This invention relates to microprocessors, and particularly relates to microprocessor integrated circuits which include an on-chip serial port.
Microprocessor designers have increasingly endeavored to improve performance in various microprocessors by increasing clock speeds and adding parallelism. Large blocks of random access memory (RAM) are included within the microprocessor for data storage and for program storage in order to reduce memory access times. Various types of input/output devices are included within a microprocessor integrated circuit in order to reduce total system chip count and cost. Serial ports are an example of a class of input/output devices that are commonly included with microprocessors. Various examples of serial ports may be found on digital signal processors available from Texas Instruments Incorporated, including TMS320C2x and TMS320C5x series of devices. Various features are included within the serial ports on these devices, such as Full-Duplex communication, double buffered data registers which allow a continuous data stream, independent framing and clocking for receive and transmit, direct interface to industry standard Codecs, Analog Interface Chips (AICs), and other serially connected A/D and D/A devices, and external shift clock generation or an internal programmable frequency shift clock.
An object of the present invention is to provide improvements in the operation and control of serial interfaces for microprocessor integrated circuits.
In general, and in a form of the present invention, a microprocessor which has a central processing unit (CPU) and an internal memory, is further equipped with serial port interface circuitry that is operable to transmit and receive data with dual phase frames, wherein each phase has a different set of parameters.
In another embodiment of the present invention, the serial port interface circuitry is further operable to select a different number of words for each phase, and further operable to selectively enable or mask particular channels.
In another embodiment of the present invention, the serial port interface circuitry further comprises clock generation circuitry that is operable to convert a multi-rate clock to a single rate clock.
In another embodiment of the present invention, the serial port interface circuitry further comprises clock generation circuitry operable to perform re-synchronization.
In another embodiment of the present invention, the serial port interface circuitry further comprises clock generation circuitry operable to generate a sample clock and timing synchronization signals from an external clock source.